Implementation of Network on Chip Frequency Distributor Model

Authors:P. SAI CHARAN, B.MALLIKHARJUN, TADI CHANDRA SEKHAR

0167-0172

Design and Implementation of Power Optimized Modified Booth Multiplier

Authors:B. S. S. V. D.K. CHAITANYA, B. P. V. V. B. NARASIMHA RAO, TADI CHANDRA SEKHAR

0173-0178

Low Latency RISC Core Implementation for Multimedia Applications

Authors:G. SARATH CHANDRA PRASAD, NAGURU BHARGAVA REDDY, TADI CHANDRA SEKHAR

0179-0184

An On Chip CORDIC Design for Fixed Angle of Rotation

Authors:DATLA HANUMA KIRAN, BASINA SATYANARAYANA, P. VARALAKSHMI

0185-0192

A Review on Low Power SPI Protocol

Authors:MANISH KUNDU, ABHIJEET KUMAR

0193-0195

Low Power and High Speed Implementation for Symmetric Convolutions Based FIR Digital Filter Structures

Authors:K. SOUJANYA, B. VENU GOPAL

0196-0203

FPGA Implementation of High Dynamic Range Imaging

Authors:ALOK KUMAR, VISHAL RAMOLA, DR. SANJAY SINGH

0204-208

Use of Dual Group Minor Input Correction Vector to minimize the Input Correction Vector Compensation error in a Fixed Width Multiplier

Authors:SREE LAKSHMI ELE, SNEHA PANDU, MADHUSUDHANA RAO KOTHARI

0209-0214

Efficient Design of Sequential Counters using Reversible Logic Gates

Authors:HARIPRASAD S.A, JAGANNATH K.B, RAVI RAJ SINGH, SAPNA UPADHYAY, SARANYA S, SOUMYA

0215-0219

A Fault Locatable Scheme based on Programmable and Multiple Twisted Ring Counters

Authors:SHAIK SHABANA AZMI, K.NEELIMA

0220-0224